Home Intel talks Terascale computing at ISSC
News

Intel talks Terascale computing at ISSC

Cyril Kowaliski
Disclosure
Disclosure
In our content, we occasionally include affiliate links. Should you click on these links, we may earn a commission, though this incurs no additional cost to you. Your use of this website signifies your acceptance of our terms and conditions as well as our privacy policy.
At the Integrated Solid State Circuits Conference in San Francisco, California, Intel has revealed more details about its prototype “Tera-scale” processor. The chip was first unveiled at the Fall Intel Developer Forum last year, but Intel is now much chattier about the chip’s inner workings and architecture.

The Tera-scale processor is an array of 80 “tiles” each containing a processing engine made up of a five-port router, two independent fully-pipelined single-precision floating-point multiply-accumulator (FPMAC) units, 3KB of single-cycle instruction memory, and 2KB of data memory. The two FPMACs are based on a Very Long Instruction Word-type design, much like Intel’s Itanium. They have nine-stage pipelines and are able to provide an aggregate 16 gigaFLOPS of performance. And thanks to the five-port router, each “tile” can communicate with other tiles at up to 80GB/s.


Tera-scale chip die. Source: Intel.

The resulting chip contains 100 million transistors, which Intel has packed into a die area of 275mm². (For reference, Intel’s Core 2 Duo has 291 million transistors and a 143mm² die size.) At 3.13GHz with a core voltage of 1V, Intel says the tera-scale chip has performance of 1.0 teraFLOPS with typical power consumption of just 98W. The design can even scale down to 310 gigaFLOPS of total performance with 11W of power draw. This low power consumption is aided by a power management system that not only allows per-tile power management based on workload, but also splits each 3mm² tile into 21 dynamically-controlled sleep regions.


Tera-scale chip power scaling. Source: Intel.

Don’t expect this chip to ever hit stores, though. Last year, Intel CEO Paul Otellini then said he believed the tera-scale chip would become available as a production product in the future. Intel has now changed its tune and says it “has no plans to bring this exact chip designed with floating point cores to market.” However, the company thinks its work with the chip is instrumental in investigating new types of processor or core functions, new interconnects, and how to best optimize software for multi-core designs. In its upcoming research, Intel says it will attempt to stack 3D memory onto the chip and even develop fancier prototypes with x86 cores.

Latest News

White House Announces New Set of Rules for Federal Agencies Using AI
News

White House Announces New Set of Rules for Federal Agencies Using AI

4 Canadian School Boards Sue Three Social Media Giants
News

4 Canadian School Boards Have Sued 3 Social Media Giants for Sabotaging Young Minds

Four of the largest school boards in Canada have filed a lawsuit against social media giants for being addictive, disrupting student learning, and harming their mental health. The lawsuit seeks...

Slothana goes parabolic
Crypto News

Traders Transfer $2.2 Million in Solana to Emerging Meme Cryptocurrency Slothana

Slothana is a Solana-based meme coin that launched four days ago and has raised over $2.2M since. Currently, you can buy 10,000 SLOTH with 1 SOL (~$188). The meme project...

Reddit Shares Fall 16% In A Day After Promoters Sell
News

Reddit Shares Fall 16% in a Day after Promoters Sell One Million Shares

Gold Miner Nilam Resources Shares Surge 22x Amidst Bitcoin Buying Announcement
Crypto News

Gold Miner Nilam Resources Shares Surge 22x Amidst Bitcoin Buying Announcement

BlackRock CEO Goes Bullish on BTC as Spot Bitcoin ETF Crosses $17 Billion
Crypto News

BlackRock CEO Goes Bullish on BTC as Spot Bitcoin ETF Crosses $17 Billion

Elliott Wave Pattern Indicates Ripple (XRP) Might Surge to $13
Crypto News

Elliott Wave Pattern Indicates Ripple (XRP) Might Surge to $13