25 Comments(s). 1 Pages(s). Showing page 1. [ 1 ]

   #25. Posted at 06:06 PM on Dec 10th 2007 Edit   Reply

Is this a hardware or a software bug?

As a hardware bug, would, or should it have been detected by AMD chip designers doing either more, or a better job, of functional simulation during the logic design phase of the development?

Or is it a software bug, that was not an error in the underlying chip and a problem that might have been exposed if AMD had done more or better emulation and running the software?

Or was it an act of God and beyond the comprehension of Man?

Inquiring minds want to know!!
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   #24. Posted at 06:51 AM on Dec 7th 2007 Edit   Reply

The beauty of opensource...You can always see the funny shit going on with the hardware! :)
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   #20. Posted at 12:05 AM on Dec 6th 2007 Edit   Reply

I don't see virtualization mentioned here. Perhaps there exists some non-virtualization workloads that can trigger the bug?
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   #6. Posted at 04:09 PM on Dec 5th 2007, Edited at 04:12 PM on Dec 5th 2007 Edit   Reply

Ouch! So it's possible for the processor to access or modify a page in memory and then it's page table entry to be moved form the L2 to the L3 cache before the processor has had a chance to up date the accessed and dirty bits in the L2 version of that page table entry, so there's now two versions of this page table entry in the cache hierarchy that conflict with each other. One said that the page has been accessed or modified and the other may say it hasn't. I think this could be the cause of the data corruption for an unrelated cache operation, if I'm reading this correctly (I understand how virtual memory systems work pretty well but I understand caches less well)

This could also be why it's a problem under high load, as the caches are being modified within this small time period between page access and these bits being updated.

This is my take on it so far.
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   #21. Posted at 12:51 AM on Dec 6th 2007 Edit   Reply

I got a movie title,

Accessed and Dirty Bits

The titillating rise and fall of a sexy processor.
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   #18. Posted at 09:20 PM on Dec 5th 2007 Edit   Reply

Am I the only one that saw "AMD does mitigate its warnings by saying few customers are actually affected by the bug." and immediately thought that this is very true, especially considering the number of people that are actually buying the Phenom chips?

Might I refresh those short term memories with the following: http://support.microsoft.com/?kbid=936357

Intel had a nasty little bug in their latest chips that had to be fixed with BIOS updates or MS patches.
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   #15. Posted at 08:05 PM on Dec 5th 2007, Edited at 08:12 PM on Dec 5th 2007 Edit   Reply

. . . and the very small number of affected customers (you know it if you have an affected part) . . .

This tells me that whatever few Phenoms and Barcelona Opterons have managed to get into the channel haven't been selling well.
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   #14. Posted at 07:37 PM on Dec 5th 2007 Edit   Reply

Fantastic. A great incentive to switch and hopefully great prices for us linux nerds :)
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   #10. Posted at 04:48 PM on Dec 5th 2007 Edit   Reply

I <3 the pic on this article.
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   #1. Posted at 03:43 PM on Dec 5th 2007 Edit   Reply

Oh, poor AMD. This is just such a PR disaster for them.

Bit of a shame that they are asking manufacturers to FORCE the microcode update on, when a) the problem is rare and b) there is a feasible software fix. By all means enable it by default, but if I had one of these early Phenoms I'd want to be able to turn the hobbling off!

Do we know if this can be fixed easily in a new stepping?
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25 Comments(s). 1 Pages(s). Showing page 1. [ 1 ]
 
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