Memory subsystem performance
We begin with some synthetic benchmarks of memory throughput, which give us a chance to look at the effect of the 3MB L2 caches on the E7200 and Q9300 processors.

Ok, so this isn't easy to see with the multitude of results graphed above, I admit, but the difference between 3MB and 6MB of L2 cache per chip becomes apparent when the Q9450's turd brown diverges from the Q9300's poop brown between the 4MB and 64MB test block sizes.

This is all very technical.

With a 1GB test block, we're basically measuring data throughput to main memory. The Q9450 outperforms the Core 2 Extreme QX9650, curiously enough (perhaps because its 2.66GHz operating frequency syncs up well with our 1333MHz FSB and DDR3 memory). The Phenoms achieve markedly higher throughput, thanks in part to their integrated memory controllers.

The Core architecture's memory disambiguation logic helps to mask memory access latency. As a result, performance in this test is partially a function of clock frequency for Core 2 processors. The Q9300 is thus somewhat slower than the Q9450 or the QX9650. The E7200, meanwhile, suffers a small penalty due to its 1066MHz bus speed. The Phenoms' memory access latencies are higher than one might expect, given their integrated memory controllers, because of the additional latency contributed by their L3 caches.

Of course, all of this stuff about latency and scatology is just technical mumbo-jumbo, with only a partial impact on real-world performance, so let's move on.